1. Field
Embodiments of the present invention relate to the field of software tools to facilitate designing computer architecture. Specifically, embodiments of the present invention relate to automatically generating register transfer level (RTL) program code from a transaction level model (TLM) description of an integrated circuit.
2. Description of the Related Art
Computer related technologies become more complex with each passing year. Thus, the design and verification of computer architectures such as systems on a chip (SoC) also become increasingly more challenging. It is desirable that the design engineer have available a tool that allows design description at a high level of abstraction. However, in order to verify the design, a description of the design is needed at a lower-level abstraction. Conventionally, converting from the high-level abstraction description to the low-level abstraction description is challenging, time consuming, and potentially error prone.
Transaction level modeling (TLM) is a technique to describe certain designs at a high level of abstraction. Transaction level modeling is typically used for designs in which protocol based communication is dominant. For example, TLM is often used for designs involving computer busses or network structures. Modeling in TLM can simplify design by reducing the amount of detail a designer must consider. The TLM design can be used by a simulator tool such as BusSimulator, which is commercially available from CoWare® of San Jose, Calif. Further, TLM can result in a fast simulation because the amount of events and information passed during simulation is reduced by the limited description details.
One lower level abstraction description that is commonly used is known as register transfer level (RTL). Unfortunately, conventionally the conversion from a TLM description to an RTL description is manual process. The manual conversion process is time consuming and error prone. Moreover, because the design and verification process involves modifying the TLM description based on the results of the verification stage, a new RTL description must be produced each time the TLM description is modified. Thus, the conventional design and verification process can be very time consuming and error prone.